Every transition from one technology node to the next technology node has led to more complex circuit design implementations in integrated circuits. Smaller transistor geometries have allowed potentially more functionality implemented per unit of integrated circuit area. At the same time, the costs of developing and manufacturing integrated circuits have also increased with every technology node. Therefore, integrated circuit developers want to verify that a gate-level representation of a circuit design behaves as defined in the design specification before manufacturing the integrated circuit. The goal is to locate and fix errors in the gate-level representation of the circuit design early such that expensive re-spins can be avoided or at least kept to a minimum.
Gate-level timing simulation has traditionally been used to perform this verification step. Gate-level timing simulation uses a test bench together with a software model of the circuit design to generate output responses to different input vectors. The test bench then compares these output responses with expected results. However, the execution time of gate-level timing simulation often exceeds any practical durations, especially for very big circuit designs that can include billions of gates. Hardware emulation or prototyping of circuit designs have emerged as a faster, more practical alternative to simulation.
Configurable integrated circuits such as programmable integrated circuits are often used as a platform for performing hardware emulation or prototyping of circuit designs. For this purpose, a circuit design description is compiled and implemented on one or more configurable integrated circuits and the test bench is executed on the one or more configurable integrated circuits. Verifying the gate-level representation of a circuit design using hardware emulation reduces execution time by several orders of magnitude compared to gate-level timing simulations.